Quick Verilog Module Isolator - Isolates a design for testing.
FPGA projects in VHDL. FPGA_CPU_Verification: an 8-bit CPU (hardwired and microprogrammed control units) with a self-checking UVVM testbench, 20,000 random instructions and coverage, run in GHDL on GitHub Actions; timing closed at 50 MHz on a Cyclone V.
A SystemVerilog-based UART (Universal Asynchronous Receiver/Transmitter) module built from scratch using FSM design. Includes baud tick generator, transmitter and receiver FSMs, and simulation testbenches for 8N1 serial communication.
Verilog-2001 & FPGA Linter aligned with Google's Verilog Style Guide.
VHDL SPI master on FPGA controlling ADMV1013/ADMV1014 microwave up/down converters
Finite state machine (FSM) design in VHDL — simulated and implemented on FPGA hardware with Intel Quartus. University project, HsH.
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