fsm-controller

Here are 6 public repositories matching this topic...

nimanaqavi / Digital_Filter

Digital Audio Noise Filtering with MATLAB and Verilog This project implements a complete end-to-end system for detecting and filtering noise from real-world audio using a combination of MATLAB signal processing and Verilog hardware design. Starting from spectral analysis and filter synthesis in MATLAB, it proceeds to fixed-point audio formatting,

fpga filter verilog digital-signal-processing audio-filter audio-processing digital-filter iir-filter fpga-programming chebyshev-filter hardware-design fsm-controller

Updated Aug 9, 2025
Verilog

Rushikesh-Dandgawhal / Alarm_Clock

Star

Digital Alarm Clock in Verilog HDL | FSM | ModelSim | Intel Quartus Prime | FPGA RTL Design

fsm fpga rtl verilog alarm-clock systemverilog vlsi modelsim digital-design quartus-prime vlsi-design vlsi-project rtl-design-and-verification alarm-clock-project fsm-controller fsm-design digital-design-verification

Updated Aug 4, 2026
Verilog

panktipatel1711 / FPGA-Based-Traffic-Light-Controller

Star

An industry-standard FPGA Traffic Light Controller designed in SystemVerilog (FSM-based) featuring an interactive Python Streamlit co-simulation control dashboard and comprehensive EPWave verification.

systemverilog hardware-simulation rtl-design streamlit-dashboard fsm-controller fpga-verification

Updated Jun 22, 2026
Verilog

usman-irshad1 / risc-v-multicycle-processor

Star

End-to-end 32-bit RISC-V (RV32I/RV32IM) Processor Architecture in SystemVerilog: 5-stage engineering progression from Digital Logic Primitives & ALU/RegFile Subsystems to Single-Cycle and FSM Multi-Cycle Cores.

fpga riscv systemverilog computer-architecture rv32im cpu-design rtl-design fsm-controller

Updated Oct 17, 2026
Verilog

panktipatel1711 / VLSI-Digital-Clock-Alarm

Star

A parameterizable and synthesizable single-clock-domain Digital Clock core with integrated Alarm, Snooze, and 12/24-hour display modes implemented in Verilog HDL. Features double-register button debouncing and a time-multiplexed 7-segment display driver.

verilog systemverilog testbench digital-clock digital-design hardware-description-language fpga-development vlsi-design rtl-design fsm-controller

Updated Jun 21, 2026
Verilog

amyretro / FPGA-Perceptron-Hardware-Accelerator

Star

Verilog-based FPGA implementation of an optimized Perceptron hardware accelerator featuring a 10-state FSM control unit and software/hardware co-design.

fpga rtl neural-networks verilog digital-design co-design hardware-accelerator fsm-controller

Updated Oct 10, 2026
Verilog

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