Synthesizable FPGA digital twin of a turbojet engine for Hardware-in-the-Loop (HIL) emulation. Features Q16.16 fixed-point arithmetic in Verilog, memory-mapped AXI4-Lite CSRs, and automated Cocotb/Python co-simulation.
python fpga dsp aerospace embedded-systems verilog vivado verilator hardware-in-the-loop cocotb digital-twin axi4-lite artix-7 fixed-point-math do-254
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Updated
Nov 13, 2026 - Python