cts

Find solutions for the Cognizant Early Engagement Program [ Continuous Skill Development ].

Passing SafetyNet with Magisk's Zygisk and DenyList

TCS, Infosys, Zoho, Freshworks, Wipro, CTS Placement Preparation Handbook 📚

legbot四足/四轮足机器人Isaac lab训练框架，包含PPO、PPO+MoE+CTS、WF-CTS-MOE（四轮足训练：真机已验证多种地形的鲁棒运动），可实现多种地形下的鲁棒运动控制。

TypeScript dual packages.

This repository presents a complete RTL-to-GDSII ASIC implementation of the PicoRV32 RISC-V processor using the Skywater 130nm (Sky130) open-source PDK. The project demonstrates an industry-standard VLSI backend flow using Cadence EDA tools, covering synthesis, placement, routing, verification, and GDSII generation.

Synthesis using Synopsys DC and Physical Design flow using Synopsys ICC II, of my RISC-V 5 stage pipelined using 32 nm tech repo

Билиотека и cli-утилита и http-сервис для работы с ботами express / express.ms

Control Frame Attack Vulnerability Detection Tool (GitLab Mirror)

Utility that allows the display of any image cropped from an external image file (Bitmap images of type jpeg,png and bmp) into any sized image on the screen in any coordinate available to the display system.

symmetric clock tree synthesis for NTV IC design

Interfacing to BCMS CTS

An installer designed to help you install the combat tests.

The ultimate enhancement for displaying of transport requests in SAP GUI

TRM - package manager for SAP ABAP with semantic versioning, dependencies, registries, CTS delivery, lockfiles, updates, and safe uninstall.

ASIC Physical Design of FIFO using Cadence Innovus | Floorplan → CTS → Routing → Timing & Power Analysis

A repository containing mods that are compatible with the combat test snapshot 8c.

Dumps of kernel sources from the conformance test runs residing in OpenCL-CTS repo

Core Node.js library for TRM, the open-source package manager for SAP ABAP, implementing package lifecycle and SAP connector workflows.

This project focuses on the design, verification, and physical implementation (RTL to GDSII) of full adder circuits using two architectural approaches: flat and hierarchical design methodologies. The entire digital ASIC flow is executed using Synopsys EDA tools, targeting a 32nm CMOS technology node.